module control_bench;
    
    reg     [4:0]   opcode;
    reg             MemRead_w,MemWrite_w,RegWrite_w;
    wire    [1:0]   RegDst;
    wire            Jump,JR,Branch,MemRead,MemtoReg,MemWrite;
    wire            ALUSrc1,ALUSrc2,RegWrite,sign_zero;
    wire            ExtMux,wb_pc,PC_en;

    control DUT (
    //  input
        .opcode(opcode),.MemRead_w(MemRead_w),
        .MemWrite_w(MemWrite_w),.RegWrite_w(RegWrite_w),
    //  output
        .RegDst(RegDst),.Jump(Jump),.JR(JR),.Branch(Branch),
        .MemRead(MemRead),.MemtoReg(MemtoReg),.MemWrite(MemWrite),
        .ALUSrc1(ALUSrc1),.ALUSrc2(ALUSrc2),
        .RegWrite(RegWrite),.sign_zero(sign_zero),
        .ExtMux(ExtMux),.wb_pc(wb_pc),.PC_en(PC_en)
    );

    integer k;
    
    initial 
    begin
        for (k=0;k<=31;k=k+1)
        begin
            opcode = k;
#5          $display("opcode %b : RegDst %b Jump %b JR %b Branch %b MemRead %b MemtoReg %b MemWrite %b ALUSrc1 %b ALUSrc2 %b RegWrite %b sign_zero %b ExtMux %b wb_pc %b PC_en %b",opcode,RegDst,Jump,JR,Branch,MemRead,MemtoReg,MemWrite,ALUSrc1,ALUSrc2,RegWrite,sign_zero,ExtMux,wb_pc,PC_en);
        end
    #20 $finish;
    end

endmodule
